PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 339

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

20.2.2
The receiver block diagram is displayed in
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
20.2.2.1
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first
bit, also known as the Start bit, is always a zero (after
accounting for RXDTP setting). Following the Start bit
will be the Least Significant bit of the data character
being received. As each bit is received, the value will
be sampled and shifted into the Receive Shift Register
(RSR). After all 8 or 9 data bits (user selectable option)
of the character have been shifted in, one final bit time
is measured and the level sampled. This is the Stop
bit, which should always be a ‘1’ (after accounting for
RXDTP setting). If the data recovery circuit samples a
‘0’ in the Stop bit position then a framing error (FERR)
is set for this character, otherwise the framing error is
cleared for this character.
Once all data bits of the character and the Stop bit has
been received, the data bits in the RSR will
immediately be transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters before
software is required to service the EUSART receiver.
The RSR register is not directly accessible by
software. Firmware can read data from the FIFO by
reading the RCREGx register. Each firmware initiated
read from the RCREGx register will advance the FIFO
by one character, and will clear the receive interrupt
flag (RCxIF), if no additional data exists in the FIFO.
20.2.2.2
If the user firmware allows the FIFO to become full,
and a third character is received before the firmware
reads from RCREGx, a buffer overrun error condition
will occur. In this case, the hardware will block the
RSR contents (the third byte received) from being
copied into the receive FIFO, the character will be lost
and the OERR status bit in the RCSTAx register will
become set. If an OERR condition is allowed to occur,
firmware must clear the condition by clearing and then
resetting CREN, before additional characters can be
successfully received.
 2011 Microchip Technology Inc.
EUSART ASYNCHRONOUS
RECEIVER
Receiving Data
Receive Overrun Error
OSC
. This mode would typically be used
Figure
20-6.
PIC18F46J11 FAMILY
20.2.2.3
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
20.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note:
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
Enable the reception by setting bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
enable bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREGx to determine if the device is
being addressed.
If the receive FIFO is overrun, no addi-
tional characters will be received until the
overrun condition is cleared.
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
Setting Up Asynchronous Receive
DS39932D-page 339