GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 100

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
V_Stop_2
Operator_Polarity_2
H_Start_3
H_Stop_3
Address
5Fh
5Fh
60h
60h
60h
60h
60h
61h
62h
36655 - 2
15-4
Bit
15
14-0
3
2
1
0
15-0
15-0
April 2006
Reserved. Set these bits to zero when writing to 60h.
Description
Reserved. Set this bit to zero when writing to 5Fh.
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER2_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Polarity_2 - Use this bit to invert the polarity of the final
USER2 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference:
AND_2 - logical operator: USER2_H AND USER2_V
Set this bit HIGH to output a signal that is only active
when both USER2_H and USER2_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference:
OR_2 - logical operator: USER2_H OR USER2_V
Set this bit HIGH to output a signal that is active
whenever USER2_H or USER2_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference:
XOR_2 - logical operator: USER2_H XOR USER2_V
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER2_H or USER2_V is active. Signal is inactive
when USER2_H and USER2_V are both active or both
inactive.
Reference:
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_3.
Reference:
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
GS4911B/GS4910B Data Sheet
R/W
–
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
Default
–
0
–
1
0
0
0
0
0
100 of 113