GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 103

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Operator_Polarity_4
Ext_Audio_Mode
Address
6Ah
6Ah
6Ah
6Ah
6Ah
81h
36655 - 2
15-4
15-0
Bit
3
2
1
0
April 2006
Reserved. Set these bits to zero when writing to 6Ah.
Polarity_4 - Use this bit to invert the polarity of the final
Set this register to 20C1h to enable the Extended Audio
Description
USER4 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference:
AND_4 - logical operator: USER4_H AND USER4_V
Set this bit HIGH to output a signal that is only active
when both USER4_H and USER4_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference:
OR_4 - logical operator: USER4_H OR USER4_V
Set this bit HIGH to output a signal that is active
whenever USER4_H or USER4_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference:
XOR_4 - logical operator: USER4_H XOR USER4_V
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER4_H or USER4_V is active. Signal is inactive
when USER4_H and USER4_V are both active or both
inactive.
Reference:
Mode of the device.
To fully enable this mode, VID_STD[5:0] must be set to
4d, and the F_Lock_Mask and V_Lock_Mask bits [4:3]
of register address 16h must be set to 1.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 16h.
Reference:
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.8.3 on page 69
Section 3.11 on page 75
GS4911B/GS4910B Data Sheet
R/W
–
R/W
R/W
R/W
R/W
R/W
Default
–
1
0
0
0
0
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