GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 79

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.12.3 Configuration and Status Registers
Table 3-13: Configuration and Status Registers
Register Name
RSVD
H_Period
H_16_Period
V_Lines
V_2_Lines
F_Lines
Address
00h - 09h
0Ah
0Bh
0Ch
0Dh
0Eh
Table 3-13
registers.
All registers are available to the host via the GSPI and are all individually
addressable.
36655 - 2
Bit
–
15-0
15-0
15-0
15-0
15-0
summarizes the GS4911B/GS4910B's internal status and configuration
April 2006
Description
Reserved.
Contains the number of 27MHz pulses in the input H
Sync period. This register is set by the Reference
Format Detector block using the H Sync signal present
on the external HSYNC input pin.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
HSYNC period is applied.
Reference:
Contains the number of 27MHz pulses in 16 H Sync
periods. This register is set by the Reference Format
Detector block using the H Sync signal present on the
external HSYNC input pin. It is useful for 1/1.001 data
detection.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
HSYNC period is applied.
Reference:
Contains the number of H Sync periods in the input V
Sync interval. This register is set by the Reference
Format Detector block using the signals present on the
external HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
VSYNC period is applied.
Reference:
Contains the number of H Sync periods in 2 V Sync
intervals. This register is set by the Reference Format
Detector block using the signals present on the external
HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a different
VSYNC period is applied.
Reference:
Contains the number of H Sync periods in the input F
Sync interval. This register is set by the Reference
Format Detector block using the signals present on the
external HSYNC and FSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference is applied. If
the new reference does not include an FSYNC pulse,
this register will be set to zero.
Reference:
Section 3.5.1 on page 45
Section 3.5.1 on page 45
Section 3.5.1 on page 45
Section 3.5.1 on page 45
Section 3.5.1 on page 45
GS4911B/GS4910B Data Sheet
R/W
–
R
R
R
R
R
Default
–
N/A
N/A
N/A
N/A
N/A
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