GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 59

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

where:
BW = the desired video PLL loop bandwidth
JITTERIN = Jitter present on applied HSYNC reference signal, in seconds
H_Feedback_Divide = the numerator of the video PLL divide ratio
H_Feedback_Divide represents the numerator of the ratio of the output clock
frequency to the frequency of the H reference pulse. It is calculated as described
in
NOTE: The bandwidth calculation represented by the above equation is only
approximate. As the programmed value of Video_Res_Genlock becomes larger,
the approximation becomes more accurate.
For example, the following steps are necessary to program a loop bandwidth of
25Hz given the following conditions: input HSYNC jitter = 3 ns, VID_STD[5:0] = 3
and input reference format = NTSC.
1. Calculate H_Feedback_Divide (as defined in
Therefore, H_Feedback_Divide = 1716.
2. Calculate the value for Video_Res_Genlock:
3. Calculate the value for Video_Cap_Genlock:
Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.
NOTE: The value programmed in the Video_Res_Genlock register must be
between 32 and 42. The value programmed in the Video_Cap_Genlock register
must be greater than 10. These limits define the exact range of loop bandwidth
adjustment available.
36655 - 2
∴
Video_Cap_Genlock
Video_Res_Genlock
f
f
------------------------------------------------- -
H_Reference_Divide
H_Feedback_Divide
pclkout
Hrefin
------------------------------------------------- -
H_Reference_Divide
H_Feedback_Divide
Section 3.6.2.1 on page
=
=
----------- - MHz
1716
27MHz
27
April 2006
=
=
×
=
f
-----------------
37 21
f
pclkout
Hrefin
47
27
–
+
×
log
1716
----------- -
27
54.
=
2
(
6 25
16
=
×
1716
----------- -
1
×
(
3 10
×
GS4911B/GS4910B Data Sheet
9 –
)
×
1716
Section 3.6.2.1 on page
)
=
37
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