GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 17

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 1-1: Pin Descriptions (Continued)
Pin
Number
51
52
53
54
55
56
57
Name
PCLK1
PCLK1&2_GND
PCLK1&2_VDD
PhS_VDD
PhS_GND
JTAG/HOST
SCLK_TCLK
Timing
–
–
–
–
–
Non
Synchronous
Non
Synchronous
36655 - 2
April 2006
Type
Output
Power
Supply
Power
Supply
Power
Supply
Power
Supply
Input
Input
Description
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK1 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK1 output pin will operate at the
fundamental frequency determined by the setting of the VID_STD[5:0]
pins. It is possible to define other non-standard fundamental clock rates
using the host interface.
It is also possible to select different division ratios for the PCLK1 output
by programming designated registers in the host interface. A clock
output of the fundamental rate, fundamental rate ÷2, or fundamental rate
÷4 may be selected.
By setting designated registers in the host interface, the current drive
capability of this pin may be set high or low. By default, the current drive
will be low. It must be set high if the clock rate is greater than 100MHz.
The PCLK1 output will be held LOW when VID_STD[5:0] = 00h.
Ground connection for PCLK1&2 circuitry. Connect to GND.
Most positive power supply connection for PCLK1&2 circuitry. Connect to
+1.8V DC.
Most positive power supply connection for the video clock phase shift
internal block. Connect to +1.8V DC.
Ground connection for the video clock phase shift internal block. Connect
to GND.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured as GSPI pins for normal host interface operation.
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
All JTAG / Host Interface address and data are shifted into/out of the
device synchronously with this clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCLK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCLK operates as the JTAG test clock, TCLK.
GS4911B/GS4910B Data Sheet
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