GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 91

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
N
(GS4911B only)
D
(GS4911B only)
RSVD
Audio_Cap_Genlock
(GS4911B only)
Audio_Res_Genlock
(GS4911B only)
A_Feedback_Divide
(GS4911B only)
a
a
Address
34h-33h
36h-35h
37h - 38h
39h
39h
3Ah
3Ah
3Ch-3Bh
36655 - 2
Bit
31-0
31-0
–
15-6
5-0
15-6
5-0
31-0
April 2006
Description
A non-zero number programmed in this register defines
the numerator for the ratio of the audio clock to the
27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary depending on
the output audio rate selected.
Address 33h = bits 15-0
Address 34h = bits 31-16
Reference:
A non-zero number programmed in this register defines
the denominator for the ratio of the audio clock to the
27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary depending on
the output audio rate selected.
Address 35h = bits 15-0
Address 36h = bits 31-16
Reference:
Reserved.
Reserved. Set these bits to zero when writing to 39h.
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
10 and Audio_Res_Genlock - 21.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
Reserved. Set these bits to zero when writing to 3Ah.
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
In the internal audio genlock block, this register defines
the numerator of the divide ratio.
This register may be programmed to manually genlock
the audio clock to the video clock.
The default value of this register will vary depending on
the output video standard selected.
Address 3Bh = bits 15-0
Address 3Ch = bits 31-16
Reference:
Section 3.9.2 on page
Section 3.9.2 on page
Section 3.6.4 on page 58
Section 3.6.4 on page 58
Section 3.6.2.2 on page 56
GS4911B/GS4910B Data Sheet
73.
73.
R/W
R/W
R/W
–
–
R/W
–
R/W
R/W
Default
–
–
–
–
–
–
–
–
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