GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 18

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 1-1: Pin Descriptions (Continued)
Pin
Number
58
59
60
61
Name
SDIN_TDI
SDOUT_TDO
CS_TMS
RESET
Timing
Synchronous
with
SCLK_TCLK
Synchronous
with
SCLK_TCLK
Synchronous
with
SCLK_TCLK
Non
Synchronous
36655 - 2
April 2006
Type
Input
Output
Input
Input
Description
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Input / Test Data Input.
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output.
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select.
Host Mode (JTAG/HOST = LOW):
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to their default settings or
to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all host registers and functional blocks will be set
to their default conditions. All input and output signals will become high
impedance, except PCLK1 and PCLK2, which will be set LOW.
When set HIGH, normal operation of the device will resume.
The user must hold this pin LOW during power-up and for a minimum of
500 uS after the last supply has reached its operating voltage.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all host registers and functional blocks will be set
to their default conditions and the JTAG test sequence will be held in
reset.
When set HIGH, normal operation of the JTAG test sequence will
resume.
GS4911B/GS4910B Data Sheet
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