GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 81
GS4910B
Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
1.GS4910B.pdf
(113 pages)
- Current page: 81 of 113
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Table 3-13: Configuration and Status Registers (Continued)
Register Name
Genlock_Status
Address
15h
15h
15h
15h
15h
15h
15h
36655 - 2
Bit
15-6
5
4
3
2
1
0
April 2006
Reserved.
Description
Reference_Lock - this bit will be HIGH when the output
is successfully genlocked to the input (i.e. when bits 4-1
of this register are HIGH and are not masked by bits 4-2
of register 16h).
The LOCK_LOST output pin is an inverted copy of this
bit.
Reference:
F_Lock - this bit will be HIGH when the output F is
successfully genlocked to the FSYNC input.
NOTE: If the input reference does not include an
FSYNC input, this bit will have the same setting as
V_Lock (bit 3).
Reference:
V_Lock - this bit will be HIGH when the output V is
successfully genlocked to the VSYNC input.
Reference:
H_Lock - this bit will be HIGH when the output H is
successfully genlocked to the HSYNC input.
Reference:
Clock_Lock - this bit will be HIGH when the video clock
is locked to the internal V_pll AND the audio clock is
locked to the internal A_pll (i.e. bits 0 and 1 of register
1Fh are HIGH).
Reference:
Reference_Present - this bit will be HIGH when a valid
input reference signal has been applied to the device.
The REF_LOST output pin is an inverted copy of this
bit.
Reference:
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.5.2 on page 45
GS4911B/GS4910B Data Sheet
R/W
–
R
R
R
R
R
R
Default
–
N/A
N/A
N/A
N/A
N/A
N/A
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