GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 89

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
PCLK2_Phase/Divide
PCLK3_Phase/Divide
PCLK3_Tristate
RSVD
Address
2Dh
2Dh
2Dh
2Dh
2Dh
2Eh
2Eh
2Eh
2Eh
2Fh
2Fh
2Fh - 30h
36655 - 2
15-2
Bit
15-7
6
5-2
1
0
15-6
5-2
1
0
1-0
–
April 2006
Reserved. Set these bits to zero when writing to 2Fh.
Description
Reserved. Set these bits to zero when writing to 2Dh.
Current_P2 - selects the current drive capability of the
PCLK2 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK2 is
greater than 100MHz.
Reference:
PCLK2_Phase - adjusts the output phase of the PCLK2
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table
Reference:
Divide_By_4 - set this bit HIGH to divide the output
PCLK2 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Divide_By_2 - set this bit HIGH to divide the output
PCLK2 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK2 pin LOW.
Reference:
Reserved. Set these bits to zero when writing to 2Eh.
PCLK3_Phase - adjusts the output phase of the
PCLK3/PCLK3 clock with respect to the timing output
pins. Phase is delayed in 700ps (nominal) increments
as shown in
Reference:
Divide_By_4 - set this bit HIGH to divide the output
PCLK3/PCLK3 by four.
Setting this bit and bit 0 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Divide_By_2 - set this bit HIGH to divide the output
PCLK3/PCLK3 by two.
Setting this bit and bit 1 simultaneously HIGH will give
the full rate video clock on the PCLK3 / PCLK3 pins.
Reference:
Set these bits to 11b to tristate the PCLK3 / PCLK3 pins.
Reference:
Reserved.
3-6.
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Table
3-6.
GS4911B/GS4910B Data Sheet
R/W
–
R/W
R/W
R/W
R/W
–
R/W
R/W
R/W
–
R/W
–
Default
–
0
0
0
0
–
0
0
0
–
00b
–
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