GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 64

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GS4910B

Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
Table 3-8: Audio Clock Divider
The fs signal on ACLK1-3 has an accurate 50% duty cycle, and can be used for
left/right definition, with the following exception: if fs = 96kHz and the user
configures the host interface such that one of the three ACLK pins is set to output
a clock signal at 192fs or 384fs, the 512fs clock will have a 33% duty cycle.
All audio clocks are initially reset on the rising edge of the AFS pulse, ensuring that
video to audio clock synchronization is correct. During normal operation, the audio
clock edge is allowed to drift slightly with respect to the AFS pulse. By default, the
audio clock will be reset directly by the AFS pulse if it drifts more than
approximately +/-0.1us from the rising edge of the AFS pulse. However, after
device reset, or after the application of a new input reference, the ACLK outputs
may sometimes be offset from the AFS pulse by up to several microseconds. The
offset will remain until the device is reset or the reference removed and re-applied.
The user may avoid this offset by minimizing the width of the AFS_Reset_Window
using bits 9-7 of register 31h for the duration of the audio PLL locking process.
Once the audio PLL is locked, bit 1 of register 1Fh will be set HIGH, and the
AFS_Reset_Window may be set as desired. See
NOTE: To maintain correct audio clock frequencies for some VESA standards, the
window tolerance shown in
setting. In this case, set the AFS_Reset_Window register to 1XX.
36655 - 2
*This setting is only available when the enable_384fs bit of the Audio_Control register is HIGH.
**512fs clock will have a 33% duty cycle when the enable_384fs bit is HIGH and fs = 96kHz.
ACLKn_fs_Multiple[3:0]
April 2006
000
001
010
011
100
101
110
111
Table 3-9
may have to be increased from its default
GS4911B/GS4910B Data Sheet
Audio Clock Frequency
Table
512fs**
192fs*
384fs*
128fs
256fs
3-9.
64fs
z-bit
fs
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