GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 45

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.4.3 Automatic Polarity Recognition
3.5 Reference Format Detector
3.5.1 Horizontal and Vertical Timing Characteristic Measurements
3.5.2 Input Reference Validity
To accommodate any standards that employ the polarity of the H and V sync
signals to indicate the format of the display, the GS4911B/GS4910B will recognize
H and V sync polarity and automatically synchronize to the leading edge.
The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the
Video_Status register. Additionally, bit 2 of this register reports the detection of
either analog or digital input timing. See
register descriptions.
The reference format detector checks the validity and analyzes the format of the
input reference signal. It is designed to accurately differentiate between 59.94 and
60Hz frame rates.
When a reference signal is applied to the designated input pins, the
GS4911B/GS4910B will analyse the signal and report the following in registers
0Ah to 0Eh of the host interface:
•
•
•
•
•
These parameters may be read via the host interface and are used by the device
to determine reference signal validity.
Before the device attempts to operate in Genlock mode, the input signals applied
to HSYNC and VSYNC must be valid and must conform to one of the 36
recognized video standards or 16 recognized graphics standards described in
Section 1.4 on page
manually programmed to genlock to a reference that is neither valid nor recognized
(see
For an input reference signal to be considered valid, the periodicity of HSYNC must
be between 9us and 70us, and the periodicity of VSYNC must be between 8ms and
50ms. The FSYNC signal is not essential for validity. For output video standards
other than VID_STD[5:0] = 62, the REF_LOST pin will be set LOW once the input
reference signal is considered valid.
36655 - 2
the number of 27MHz clock pulses between leading edges of the H input
reference signal (H_Period register)
the number of 27MHz clock pulses in 16 horizontal periods (H_16_Period
register)
the number of H reference pulses between leading edges of the V input
reference signal (V_Lines register)
the number of H reference pulses in two vertical periods (V_2_Lines register)
the number of H reference pulses in one F period (F_Lines register)
Section 3.10.1 on page
April 2006
20. Alternatively, if VID_STD[5:0] = 62, the device may be
74).
GS4911B/GS4910B Data Sheet
Section 3.12.3 on page 79
for detailed
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