GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 26

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 1-3: Output Timing Signals (Continued)
Signal Name
V Sync
V Blanking
F Sync
Description
The V Sync timing signal has a leading edge at the start of the vertical sync
pulse. Its length is determined by the selected video standard (see
or according to custom timing parameters programmed in the host interface
(see
The leading edge of V Sync is nominally simultaneous with the leading edge of
the first broad pulse.
When in Genlock mode, the output V Sync signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
page
By default, after system reset, the polarity of the V Sync signal output will be
active LOW. The polarity may be selected as active HIGH by programming the
Polarity register at address 56h of the host interface (see
page
The V Blanking signal is used to indicate the portion of the video field/frame not
containing active video lines.
The V Blanking signal will be LOW (default polarity) for the portion of the
field/frame containing valid video data, and will be HIGH throughout the vertical
blanking period.
The width of this signal will be determined by the selected video standard (see
Table
interface (see
When in Genlock mode, the output V Blanking signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
page
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see
NOTE: When VID_STD = 4, 6, or 8, the Vblank output pulse width is 2 lines too
long for field 1 and 1 line too short for field 2 when compared to the digital timing
defined in ITU-R BT.656 and ITU-R BT.799.
The F Sync signal is used to indicate field 1 and field 2 for interlaced video
formats.
The F Sync signal will be HIGH (default polarity) for the entire period of field 1. It
will be LOW for all lines in field 2 and for all lines in progressive scan systems.
The width and timing of this signal will be determined by the V Sync parameters
of the selected video standard (see
timing parameters programmed in the host interface (see
page
Sync.
When in Genlock mode, the output F Sync signal will be phase locked to the
reference FSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see
page
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see
Section 3.10 on page
37).
79).
37).
74). The F Sync signal always changes state on the leading edge of V
37).
1-2), or according to custom timing parameters programmed in the host
36655 - 2
Section 3.10 on page
April 2006
74).
Table
74).
1-2), or according to custom V Sync
Section 3.12.3 on page
Section 3.12.3 on page
Section 3.12.3 on
Section 3.10 on
GS4911B/GS4910B Data Sheet
Section 3.2.1.1 on
Section 3.2.1.1 on
Section 3.2.1.1 on
Table
1-2),
79).
79).
Default Output Pin
TIMING_OUT_3
TIMING_OUT_4
TIMING_OUT_5
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