GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 74

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.10 Custom Output Timing Signal Generation
3.10.1 Custom Input Reference
In addition to the devices’s pre-programmed output timing signals, the user may
also build their own custom timing signals. This is achieved by setting
VID_STD[5:0] = 62 and programming designated host registers.
When programming custom output timing signals, the user must define the pixel,
line, and field/frame timing parameters using registers 4Eh to 55h of the host
interface (see
line 1 of the video field. The user may delay the VSync pulse to any line using the
V_Offset register (see Section 3.2.1.1).
When the user sets VID_STD[5:0] = 62, registers 4Eh to 55h will become
read/write configurable and the device will initially continue to output timing signals
based on the video format previously selected. Once the user has programmed all
eight custom timing registers, generation of the new timing signals will begin.
The frequency of the video clock will remain as previously selected unless
otherwise modified as described in
NOTE: If VID_STD[5:0] = 62 on power-up, the initial output timing signals will be
set to the internal default timing of the chip until the user programs 4Eh to 55h.
H Blanking
V Blanking
Figure 3-12: Custom Timing Parameters
As explained in
only verify that a stable signal with a period of less than 2.4ms is present on the
HSYNC input pin before attempting to genlock. Therefore, in addition to
programming custom output timing signals, the user may genlock the output timing
signals to a custom reference pulse applied to HSYNC. In this case the user is
required to manually program the video genlock block (see
page
36655 - 2
H Sync
V Sync
54).
April 2006
Figure
Section 3.5.2 on page
Lines_Per_Vsync (53h)
Clocks_Per_Hsync (4Fh)
3-12). For all custom formats, the VSync output will start on
Vsync_To_First_Active_Line (54h)
Hsync_To_SAV (50h)
Section 3.9.1 on page
Vsync_To_Last_Active_Line (55h)
45, when VID_STD[5:0] = 62, the device will
Clocks_Per_Line (4Eh)
Lines_Per_Field (52h)
Hsync_To_EAV (51h)
GS4911B/GS4910B Data Sheet
72.
Section 3.6.2.1 on
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