GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 82

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Genlock_Control
Output_H_Reset
Address
16h
16h
16h
16h
16h
16h
16h
16h
17h
36655 - 2
15-7
15-0
Bit
6
5
4
3
2
1
0
April 2006
Reserved. Set these bits to zero when writing to 16h.
When the output is genlocked to the input, the input
Description
Update_Custom_V_Clock - this bit is used to update the
custom video clock parameters programmed in registers
20h to 23h of the host interface. All non-zero
parameters in these registers will be updated via a LOW
to HIGH transition on this bit.
This bit is also used to enable the Extended Audio Mode
of the device.
Genlock_From_Host - set this bit HIGH to enable video
genlock control via the Host Interface instead of the
external GENLOCK pin (see bit 0 of this register).
Reference:
F_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of F_Lock (bit
4 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
V_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of V_Lock (bit
3 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
H_Lock_Mask - if this bit is set HIGH, the
GS4911B/GS4910B will ignore the status of H_Lock (bit
2 of register 15h) when determining the status of
Reference_Lock (bit 5 of register 15h).
Reference:
Drift_Crash - when this bit is set HIGH, the generated
video clock will drift lock to a new input reference rather
than crash lock.
Reference:
GENLOCK - this bit may be used instead of the external
pin to Genlock the output video format to the input
reference. This bit will be ignored if bit 5 of this register
is LOW.
Reference:
reference is used to reset the line-based counter
controlling the generated timing output signals.
Programming this register to a non-zero value will
over-ride the internal pixel-based counter. The counter
reset will occur every Output_H_Reset lines instead of
on a frame basis.
This register is programmed when manually
programming the internal video genlock block.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Section 3.2 on page 36
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.6.1 on page 50
Section 3.6.3 on page 58
Section 3.2 on page 36
Section 3.6.2 on page 54
GS4911B/GS4910B Data Sheet
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
–
0
0
0
0
0
0
0
–
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