GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 84

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
10FID_AFS_Reset
H_Offset
V_Offset
Address
1Ah
1Ah
1Ah
1Ah
1Ah
1Bh
1Ch
36655 - 2
15-4
Bit
3
2
1
0
15-0
15-0
April 2006
Reserved. Set these bits to zero when writing to 1Ah.
Description
AFS_Reset (GS4911B only) - set this bit HIGH to use
Reset_Sync (bit 0 of register 1Ah) to reset the output
AFS pulse.
NOTE: This bit will remain LOW in the GS4910B. Set
this bit LOW when writing to address 1Ah of the
GS4910B.
Reference:
10FID_Reset - set this bit HIGH to use Reset_Sync (bit
0 of register 1Ah) to reset the output 10FID pulse.
NOTE: If a 10FID input signal is not provided to the
device, the user must generate a reset using this bit to
initiate the 10FID timing output. In this case, the 10FID
input pin must be grounded.
Reference:
Reserved. Set this bit to zero when writing to 1Ah.
Reset_Sync - resets the pulses described in bits 2, and
3 above.
The reset pulse is generated if this bit is pulsed (LOW to
HIGH to LOW) during the output frame immediately
prior to the frame the reset is to occur. This reset will
operate independently of any other resets, for example
from the reference input.
The output H signal may be delayed with respect to the
input reference by the number of pixels programmed in
this register. (See
The value programmed in this register should not
exceed the maximum number of clock periods per line
of the outgoing standard. Horizontal advances may be
achieved by programming a value equal to the
maximum allowable offset minus the desired advance.
NOTE: This register is internally read by the device
once per field. At that time any new value programmed
is sent to the internal offset circuitry.
Reference:
The output V signal may be delayed with respect to the
input reference by the number of lines programmed in
this register. (See
The value programmed in this register should not
exceed the maximum number of lines per frame of the
outgoing standard. Vertical advances may be achieved
by programming a value equal to the maximum
allowable offset minus the desired advance.
NOTE: This register is internally read by the device
once per field. At that time any new value programmed
is sent to the internal offset circuitry.
Reference:
Section 3.7.2.1 on page 65
Section 3.7.2.1 on page 65
Section 3.2.1.1 on page 37
Section 3.2.1.1 on page 37
Section 3.2.1.1 on page
Section 3.2.1.1 on page
GS4911B/GS4910B Data Sheet
37).
37).
R/W
–
R/W
R/W
–
R/W
R/W
R/W
Default
–
0
0
–
0
0
0
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