GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 96

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Lines_Per_Field
Lines_Per_Vsync
Vsync_To_First_Active_Line
Vsync_To_Last_Active_Line
Address
52h
53h
54h
55h
36655 - 2
15-0
15-0
Bit
15-0
15-0
April 2006
Contains the number of lines per field for the selected
Contains the number of lines per active V Sync interval
Contains the number of lines from the start of V Sync to
Contains the number of lines from the start of V Sync to
Description
output timing format.
This register is 15.1 encoded (i.e. bit 0 represents 0.5
when set HIGH and 0 when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE: When bit 0 of this register is programmed HIGH,
the device assumes an interlaced output. Otherwise it
assumes a progressive output. For example,
programming ‘262.5’d will result in an interlaced output
standard with 525 lines per frame. Programming ‘525’d
will result in a progressive output with 525 lines per
frame.
Reference:
for the selected output timing format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
Reference:
the start of active video for the selected output timing
format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE1: The value programmed in this register will be
increased by 1 by the device such that V Blanking signal
generated will be one line longer than programmed.
NOTE2: For the pre-programmed output video
standards 3, 5, and 7, the value contained in this
register is incorrectly reported as 17 lines, although the
actual timing produced is correct at 16 lines.
Reference:
the end of active video for the selected output timing
format.
This register is 15.1 encoded (i.e. bit 0 represents '0.5'
when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing signals.
Otherwise, this register is read-only.
NOTE: The user cannot specify a custom vertical
blanking signal to end in the middle of a line. If this
occurs, the device will automatically adjust the timing of
the signal to fall at the beginning of the next line.
Reference:
Section 3.10 on page 74
Section 3.10 on page 74
Section 3.10 on page 74
Section 3.10 on page 74
GS4911B/GS4910B Data Sheet
R/W
R/W
R/W
R/W
R/W
Default
–
–
–
–
96 of 113