GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 58

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.6.3 Adjustable Locking Time
3.6.4 Adjustable Loop Bandwidth
3.6.4.1 Loop Bandwidth of the Video PLL
The GS4911B/GS4910B offers two different locking mechanisms to allow the user
to control the PLL lock time and the integrity of the output signal during the locking
process. The locking process is said to take place after the application of the input
reference and before the LOCK_LOST signal is set LOW.
By default, the internal PLL will crash lock. This locking process will ensure a
minimum PLL locking time; however, crash lock will cause the phase of the output
clock and timing signals to jump during the locking process. The crash behaviour
of the video PLL is controlled by the Crash_Time bits of register address 24h.
Alternatively, the user may set bit 1 of register 16h HIGH to force the PLL to drift
lock. Drift lock will increase the locking time of the PLL, but will maintain the signal
integrity of the output clock and timing pulses during the locking process.
As discussed in
the reference is removed and subsequently re-applied during Genlock mode.
The default loop bandwidth of the GS4911B/GS4910B's internal video PLL is 10Hz
when the output video standard is the same as the input reference format. For
other cross-locking combinations, the default loop bandwidth may be smaller than
1Hz or as large as 30Hz.
The user may adjust the loop bandwidth of both the video and audio PLLs to a
value that depends on the input, output, and audio standards selected, as well as
on the amplitude of the jitter present on the applied HSYNC signal. Increasing the
loop bandwidth will result in a shorter PLL lock time, but will allow more frequency
components of jitter to be passed to the outputs. Decreasing the loop bandwidth
will decrease the output jitter, but will result in a longer PLL lock time.
The capacitive component of the filter controlling the video loop bandwidth is
determined by the Video_Cap_Genlock register and the resistive component is
determined by the Video_Res_Genlock register. These two registers are located
at addresses 26h and 27h, respectively, of the host interface.
To determine the setting of Video_Res_Genlock and Video_Cap_Genlock, the
following equations must be solved:
36655 - 2
Video_Res_Genlock
Video_Cap_Genlock Video_Res_Genlock 21
April 2006
Section 3.5.3 on page
≤
=
47
+
log
2
(
6 BW JITTERIN H_Feedback_Divide
×
–
×
47, the device will normally drift lock when
GS4911B/GS4910B Data Sheet
×
)
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