GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 15

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 1-1: Pin Descriptions (Continued)
Pin
Number
41
42
43
45
Name
TIMING_OUT_6
TIMING_OUT_7
TIMING_OUT_8
LVDS/PCLK3_VDD
Timing
Synchronous
with PCLK1 ~
PCLK3
Synchronous
with PCLK1 ~
PCLK3
Synchronous
with PCLK1 ~
PCLK3
–
36655 - 2
April 2006
Type
Output
Output
Output
Power
Supply
Description
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
NOTE: Default output is F digital.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
NOTE: Default output is 10 Field ID (10FID).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See
NOTE: Default output is Display Enable (DE).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Most positive power supply connection for PCLK3 output circuitry and
LVDS driver. Connect to +1.8V DC.
Section 1.5 on page 25
Section 1.5 on page 25
Section 1.5 on page 25
GS4911B/GS4910B Data Sheet
for signal descriptions.
for signal descriptions.
for signal descriptions.
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