S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 127

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1. Read: Anytime.
2.3.32
Freescale Semiconductor
Address 0x024B
Write: Anytime.
DDRS
RDRS
Field
Field
Reset
7-0
7-0
W
R
Port S data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port S pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port S reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
RDRS7
Port S Reduced Drive Register (RDRS)
0
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTS or PTIS registers, when changing the
DDRS register.
RDRS6
0
6
Figure 2-30. Port S Reduced Drive Register (RDRS)
Table 2-28. DDRS Register Field Descriptions
Table 2-29. RDRS Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
RDRS5
0
5
RDRS4
NOTE
0
4
Description
Description
RDRS3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
RDRS2
0
2
Access: User read/write
RDRS1
0
1
RDRS0
0
0
127
(1)