S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 133

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Freescale Semiconductor
DDRM
DDRM
DDRM
DDRM
DDRM
Field
4
3
2
1
0
Port M data direction—
This register controls the data direction of pin 4.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration
of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 3.
The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the configuration of the
enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 2.
The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the configuration of the enabled
routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 1.
The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 0.
The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRM register.
Table 2-35. DDRM Register Field Descriptions (continued)
MC9S12XE-Family Reference Manual Rev. 1.25
NOTE
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
133