S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 378

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Chapter 10 XGATE (S12XGATEV3)
10.4.5
Upon detecting an error condition caused by erratic application code, the XGATE module will
immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There
are three error conditions:
All opcodes which are not listed in section
opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
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•
•
Execution of an illegal opcode
Illegal opcode fetches
Illegal load or store accesses
Software Error Detection
When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS
instruction, the XGATE prefetches and discards the opcode of the following
instruction. The XGATE will perform its software error handling actions
(see above) if this opcode fetch is illegal.
Figure 10-25. Algorithm for Locking and Releasing Semaphores
S12X_CPU
1 ⇒ XGSEM[n]
0 ⇒ XGSEM[n]
XGSEM[n] 1?
sequence
critical
.........
.........
code
MC9S12XE-Family Reference Manual Rev. 1.25
Section 10.8, “Instruction Set”
NOTE
XGATE
sequence
critical
CSEM
SSEM
.........
.........
BCC?
code
are illegal opcodes. Illegal
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