S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 141

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1. Read: Anytime.
1. Read: Anytime.
2.3.50
2.3.51
Freescale Semiconductor
Address 0x025D
Address 0x025E
Write: Anytime.
Write: Anytime.
Read: Anytime.
PPSP
Field
Field
PIEP
Reset
Reset
7-0
7-0
W
W
R
R
Port P pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-
up or pull-down device if enabled.
1 A rising edge on the associated Port P pin sets the associated flag bit in the PIFP register. A pull-down device is
0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register.A pull-up device is
Port P interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
PPSP7
PIEP7
Port P Polarity Select Register (PPSP)
Port P Interrupt Enable Register (PIEP)
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
0
0
7
7
PPSP6
PIEP6
0
0
6
6
Figure 2-49. Port P Interrupt Enable Register (PIEP)
Figure 2-48. Port P Polarity Select Register (PPSP)
Table 2-46. PPSP Register Field Descriptions
Table 2-47. PPSP Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
PPSP5
PIEP5
0
0
5
5
PPSP4
PIEP4
0
0
4
4
Description
Description
PPSP3
PIEP3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PPSP2
PIEP2
0
0
2
2
Access: User read/write
Access: User read/write
PPSP1
PIEP1
0
0
1
1
PPSP0
PIEP0
0
0
0
0
141
(1)
(1)