S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 308

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Chapter 8 S12X Debug (S12XDBGV3) Module
8.1.5
8.2
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
8.3
8.3.1
A summary of the registers associated with the S12XDBG sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
308
(See DUG)
(See DUG)
(See DUG)
Pin Name
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU12X BUS
XGATE BUS
TAGLO
TAGLO
TAGHI
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Memory Map and Registers
Block Diagram
Module Memory Map
Tagging Enable
Pin Functions
Unconditional
Table 8-4. External System Pins Associated With S12XDBG
TAGLO
TAGHI
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 8-1. Debug Module Block Diagram
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
MATCH0
MATCH1
MATCH2
MATCH3
CONTROL
TRIGGER
LOGIC
TAG &
Description
TRIGGER
STATE
BREAKPOINT REQUESTS
CPU12X & XGATE
STATE SEQUENCER
Table
TRACE BUFFER
TAGS
Freescale Semiconductor
STATE
8-2. Detailed
TRACE
CONTROL
TRIGGER