S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 275

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

6.5
6.5.1
After system reset, software should:
6.5.2
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).
Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).
Enable I maskable interrupts by clearing the I bit in the CCR.
Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to
14
Service interrupt, e.g., clear interrupt flags, copy data, etc.
Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
Process data
Return from interrupt by executing the instruction RTI
Initialization/Application Information
for an example using up to three nested interrupt requests).
Initialization
Interrupt Nesting
MC9S12XE-Family Reference Manual Rev. 1.25
Chapter 6 Interrupt (S12XINTV2)
Figure 6-
275