S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 265

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

6.3
This section provides a detailed description of all registers accessible in the XINT module.
6.3.1
Table 6-3
Freescale Semiconductor
Memory Map and Register Definition
gives an overview over all XINT module registers.
Module Memory Map
0x0122–0x0125
Address
0x012A
0x012B
0x012C
0x012D
0x012E
0x0120
0x0121
0x0126
0x0127
0x0128
0x0129
0x012F
MC9S12XE-Family Reference Manual Rev. 1.25
Interrupt Request Configuration Address Register
Interrupt Request Configuration Data Register 0
Interrupt Request Configuration Data Register 1
Interrupt Request Configuration Data Register 2
Interrupt Request Configuration Data Register 3
Interrupt Request Configuration Data Register 4
Interrupt Request Configuration Data Register 5
Interrupt Request Configuration Data Register 6
Interrupt Request Configuration Data Register 7
XGATE Interrupt Priority Configuration Register
Table 6-3. XINT Memory Map
Interrupt Vector Base Register (IVBR)
(INT_CFDATA0)
(INT_CFDATA1)
(INT_CFDATA3)
(INT_CFDATA4)
(INT_CFDATA5)
(INT_CFDATA6)
(INT_CFDATA7)
(INT_CFADDR)
(INT_XGPRIO)
(INT_CFDATA2
RESERVED
RESERVED
Use
Chapter 6 Interrupt (S12XINTV2)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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