S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 234

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Chapter 4 Memory Protection Unit (S12XMPUV1)
4.3.1.6
1. initialized as set for descriptor 0 only, cleared for all others
2. initialized as set for descriptor 0 only, if MSTR3 is implemented on the device
Read: Anytime
Write: Anytime
A descriptor can be configured as valid for more than one bus-master at the same time by setting multiple
Master select bits to one. Setting all Master select bits of a descriptor to zero disables the descriptor.
4.3.1.7
Read: Anytime
Write: Anytime
234
Address: Module Base + 0x0006
Address: Module Base + 0x0007
LOW_ADDR[
Reset
Reset
MSTR0
MSTR1
MSTR2
MSTR3
22:19]
Field
3–0
7
6
5
4
W
W
R
R
MSTR0
1
MPU Descriptor Register 0 (MPUDESC0)
MPU Descriptor Register 1 (MPUDESC1)
Master 0 select bit — If this bit is set the descriptor is valid for bus master 0 (CPU in supervisor state).
Master 1 select bit — If this bit is set the descriptor is valid for bus master 1 (CPU in user state).
Master 2 select bit — If this bit is set the descriptor is valid for bus master 2 (XGATE).
Master 3 select bit — If this bit is set the descriptor is valid for bus master 3.
Memory range lower boundary address bits — The LOW_ADDR[22:19] bits represent bits [22:19] of the
global memory address that is used as the lower boundary for the described memory range.
0
7
(1)
7
MSTR1
1
0
6
6
1
Figure 4-8. MPU Descriptor Register 0 (MPUDESC0)
Figure 4-9. MPU Descriptor Register 1 (MPUDESC1)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 4-8. MPUDESC0 Field Descriptions
MSTR2
1
0
5
5
1
MSTR3
LOW_ADDR[18:11]
1
0
4
(2)
4
Description
0
0
3
3
LOW_ADDR[22:19]
0
0
2
2
Freescale Semiconductor
0
0
1
1
0
0
0
0