S912XEG128J2MAL Freescale Semiconductor, S912XEG128J2MAL Datasheet - Page 375

• Manufacturer Part Number: S912XEG128J2MAL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH 16K RAM
• Manufacturer: Freescale Semiconductor

Specifications of S912XEG128J2MAL

• Rohs: yes
• Core: RISC
• Processor Series: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 12 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Data Rom Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Chapter 10 XGATE (S12XGATEV3)
The programmer’s model of the XGATE RISC core is shown in
Figure
10-22. The processor offers a set
of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An
additional eighth register (R0) is tied to the value “$0000”. Registers R1 and R7 have additional
functionality. R1 is preloaded with the initial data pointer of the channel’s service request vector (see
Figure
10-23). R7 is either preloaded with the content of XGISP74 if the interrupt priority of the current
channel is in the range 7 to 4, or it is with preloaded the content of XGISP31 if the interrupt priority of the
current channel is in the range 3 to 1. The remaining general purpose registers will be reset to an
unspecified value at the beginning of each thread.
The 16 bit program counter allows the addressing of a 64 kbyte address space.
The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and
the carry bit (C). The initial content of the condition code register is undefined.
10.4.3
Memory Map
The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks
within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed
information.
The XGATE vector block assigns a start address and a data pointer to each XGATE channel. Its position
in the XGATE memory map can be adjusted through the XGVBR register (see
Section 10.3.1.7, “XGATE
Vector Base Address Register
(XGVBR)”).
Figure 10-23
shows the layout of the vector block. Each vector
consists of two 16 bit words. The first contains the start address of the service routine. This value will be
loaded into the program counter before a service routine is executed. The second word is a pointer to the
service routine’s data space. This value will be loaded into register R1 before a service routine is executed.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
375