DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 101

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

17.2.1.1 T1 Mode
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a
full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel
(A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions
for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1–TS12.
The framer will load the contents of TS1–TS12 into the outgoing shift register every other D4
multiframe. In D4 mode the host should load new contents into TS1–TS12 on every other multiframe
boundary and no later than 120µs after the boundary.
17.2.1.2 E1 Mode
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common
channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two
different channel number schemes in E1. In channel numbering, TS0 through TS31 are labeled channels 1
through 32. In phone-channel numbering, TS1 through TS15 are labeled channel 1 through channel 15,
and TS17 through TS31 are labeled channel 15 through channel 30.
Table 17-1. Time Slot Numbering Schemes
Channel
Channel
Phone
TS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
101 of 269
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DS21455/DS21458 Quad T1/E1/J1 Transceivers