DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 113

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

19. CHANNEL BLOCKING REGISTERS
The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel
blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced high or
low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications. When the appropriate bits are set to a one, the RCHBLK and
TCHBLK pin will be held high during the entire corresponding channel time. Channels 25 through 32 are
ignored when the device is operated in the T1 mode.
Also, the DS21455/DS21458 can internally generate and output a bursty clock on a per-channel basis (N
x 64kbps / 56kbps). See the Fractional T1/E1 Support section.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
CH16
CH8
7
0
7
0
CH15
CH7
RCBR1
Receive Channel Blocking Register 1
88h
RCBR2
Receive Channel Blocking Register 2
89h
6
0
6
0
CH14
CH6
5
0
5
0
CH13
CH5
4
0
4
0
113 of 269
CH12
CH4
3
0
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CH11
CH3
2
0
2
0
CH10
CH2
1
0
1
0
CH1
CH9
0
0
0
0