DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 114
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
- Current page: 114 of 269
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16).
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
CH24
CH32
CH16
CH8
7
0
7
0
7
0
7
0
CH23
CH31
CH15
CH7
RCBR3
Receive Channel Blocking Register 3
8Ah
RCBR4
Receive Channel Blocking Register 4
8Bh
TCBR1
Transmit Channel Blocking Register 1
8Ch
TCBR2
Transmit Channel Blocking Register 2
8Dh
6
0
6
0
6
0
6
0
CH22
CH30
CH14
CH6
5
0
5
0
5
0
5
0
CH21
CH29
CH13
CH5
4
0
4
0
4
0
4
0
114 of 269
CH20
CH28
CH12
CH4
3
0
3
0
3
0
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CH19
CH27
CH11
CH3
2
0
2
0
2
0
2
0
CH18
CH26
CH10
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH1
CH9
0
0
0
0
0
0
0
0
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