DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 167

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver.
When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and
TRING outputs instead of a normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7  0, then the device
will force TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should
be set to zero for normal operation of the device.
Bit 1/Short Circuit Limit Disable (ETS = 1) (SCLD). Controls the 50mA (RMS) current limiter.
Bit 2/Unused, must be set to zero for proper operation.
Bit 3/Jitter Attenuator MUX (JAMUX). Controls the source for JACLK.
Bit 4/Transmit Unframed All Ones (TUA1). The polarity of this bit is set such that the device will transmit an all ones
pattern on power-up or device reset. This bit must be set to a one to allow the device to transmit data. The transmission of this
data pattern is always timed off of the JACLK.
Bit 5/Insert BPV (IBPV). A zero-to-one transition on this bit will cause a single BPV to be inserted into the transmit data
stream. Once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted.
Bit 6/Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock
recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and
set again for a subsequent reset.
Bit 7/E1/T1 Select (ETS).
0 = enable 50mA current limiter
1 = disable 50mA current limiter
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
0 = T1 Mode Selected
1 = E1 Mode Selected
ETS
7
0
LIRST
LIC2
Line Interface Control 2
79h
6
0
IBPV
5
0
TUA1
4
0
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JAMUX
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
—
2
0
SCLD
1
0
CLDS
0
0