DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 216

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT
The
SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z,
CLAMP, and IDCODE. The DS21455/DS21458 contain the following as required by IEEE 1149.1
Standard Test-Access Port and Boundary-Scan Architecture:
 Test Access Port (TAP)
 TAP Controller
 Instruction Register
 Bypass Register
 Boundary Scan Register
 Device Identification Register
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 35-1. JTAG Functional Block Diagram
DS21455/DS21458
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V
DD
JTDI
10k 
IEEE
V
DD
JTMS
TEST ACCESS PORT
BOUNDRY SCAN
IDENTIFICATION
1149.1
CONTROLLER
INSTRUCTION
REGISTER
REGISTER
REGISTER
REGISTER
BYPASS
JTCLK
design
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V
DD
JTRST
supports
DS21455/DS21458 Quad T1/E1/J1 Transceivers
SELECT
OUTPUT ENABLE
MUX
the
standard
JTDO
instruction
codes