DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 24

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Signal Name:
Signal Description:
Signal Type:
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.
Signal Name:
Signal Description:
Signal Type:
Buffered recovered clock from the network. This pin is normally tied to RCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function.
5.3 Parallel Control Port Pins
Signal Name:
Signal Description:
Signal Type:
Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.
Signal Name:
Signal Description:
Signal Type:
A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21455/DS21458 register set. A reset clears all
configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will tri-state all output and I/O
pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
BPCLK
Backplane Clock
Output
RPOSO
Receive Positive-Data Output
Output
RNEGO
Receive Negative-Data Output
Output
RCLKO
Receive Clock Output
Output
RPOSI (DS21455 Only)
Receive Positive Data Input
Input
RNEGI (DS21455 Only)
Receive Negative Data Input
Input
RCLKI (DS21455 Only)
Receive Clock Input
Input
INT
Interrupt
Output
TSTRST
Tri-State Control and Device Reset
Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers