DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 13

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

2.6 System Interface
2.7 HDLC Controllers
2.8 Test and Diagnostics
 Dual two-frame, independent receive and transmit elastic stores
 Supports T1 to E1 conversion
 Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
 Programmable output clocks for fractional T1, E1, H0, and H12 applications
 Interleaving PCM bus operation with rates of 4.096MHz, 8.192MHz, and 16.384MHz
 Hardware-signaling capability
 Access to the data streams in between the framer/formatter and the elastic stores (DS21455)
 User-selectable synthesized clock output
 Two independent HDLC controllers
 Fast load and unload features for FIFOs
 SS7 support for FISU transmit and receive
 Independent 128-byte Rx and Tx buffers with interrupt support
 Access FDL, Sa, or single/multiple DS0 channels
 DS0 access includes Nx64 or Nx56
 Compatible with polled or interrupt-driven environments

 Programmable Bit Error Rate Testing (BERT)
 Pseudorandom patterns including QRSS
 User-defined repetitive patterns
 Daly pattern
 Error insertion for single bit or continuous
 Insertion options include continuous and absolute number with selectable insertion rates
 Total-bit and errored-bit counters
 Payload Error Insertion
 Errors can be inserted over the entire frame or selected channels
 F-bit corruption for line testing

 Independent control and clocking
 Controlled-slip capability with status
 Minimum-delay mode supported
 Receive-signaling reinsertion to a backplane, multiframe sync
 Availability of signaling in a separate PCM data stream
 Signaling freezing
Bit Oriented Code (BOC) support
Loopbacks (remote, local, analog, and per-channel payload loopback)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers