DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 20
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
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5. PIN FUNCTION DESCRIPTION
5.1 Transmit Side Pins
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.
Signal Name:
Signal Description:
Signal Type:
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on
the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a
gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is
disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the
transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for
locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic-store function
is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See the Interleaved PCM Bus
Operation section for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
Signal Name:
Signal Description:
Signal Type:
Demand clock for the transmit link data [TLINK] input.
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-
bit position (D4) or the Z-bit position (ZBTSI) or any combination of the Sa bit positions (E1).
TCLK
Transmit Clock
Input
TSER
Transmit Serial Data
Input
TCHCLK
Transmit Channel Clock
Output
TCHBLK
Transmit Channel Block
Output
TSYSCLK
Transmit System Clock
Input
TLCLK
Transmit Link Clock
Output
TLINK
Transmit Link Data
Input
20 of 269
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