DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 168

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (Customer Disconnect Indication
Signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK.
Bit 1/Transmit Synchronization G.703 Clock Enable (TSCLKE).
Bit 2/Receive Synchronization G.703 Clock Enable (RSCLKE).
Bits 3 to 4/Monitor Mode (MM0 to MM1).
Bit 5/Receive Clock Edge Select (RCES). Selects which RCLKO edge to update RPOSO and RNEGO.
Bit 6/Transmit Clock Edge Select (TCES). Selects which TCLKI edge to sample TPOSI and TNEGI.
Bit 7/Unused, must be set to zero for proper operation.
MM1
0
0
1
1
0 = disabled
1 = enabled
0 = disable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
1 = enable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock
0 = disable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
1 = enable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode
0 = update RPOSO and RNEGO on rising edge of RCLKO
1 = update RPOSO and RNEGO on falling edge of RCLKO
0 = sample TPOSI and TNEGI on falling edge of TCLKI
1 = sample TPOSI and TNEGI on rising edge of TCLKI
MM0
0
1
0
1
—
7
0
Normal operation (no boost)
INTERNAL LINEAR
GAIN BOOST (dB)
TCES
LIC3
Line Interface Control 3
7Ah
6
0
20
26
32
RCES
5
0
MM1
4
0
168 of 269
MM0
3
0
RSCLKE
DS21455/DS21458 Quad T1/E1/J1 Transceivers
2
0
TSCLKE
1
0
TAOZ
0
0