DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 206

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when
the device decodes an ESI3 address during a bus read operation.
Bit 3/Unused, must be set to zero for proper operation.
Bits 4 to 6/Address ESI4 Data Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status is to be output when
the device decodes an ESI4 address during a bus-read operation.
Bit 7/Unused, must be set to zero for proper operation.
ESI4SEL2
ESI3SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ESI4SEL1
ESI3SEL1
7
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ESI4SEL2
ESIBCR2
Extended System Information Bus Control Register 2
B1h
6
0
ESI4SEL0
ESI3SEL0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
ESI4SEL1
5
0
T1 MODE
T1 MODE
SIGCHG
SIGCHG
ESSLIP
ESSLIP
RYEL
RYEL
LDN
LDN
RBL
LUP
RBL
LUP
STATUS OUTPUT
STATUS OUTPUT
ESI4SEL0
4
0
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E1 MODE
E1 MODE
V52LNK
SIGCHG
V52LNK
SIGCHG
ESSLIP
ESSLIP
RDMA
RDMA
RUA1
RUA1
RRA
RRA
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ESI3SEL2
2
0
ESI3SEL1
1
0
ESI3SEL0
0
0

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