DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 54

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM).
Bit 1/Receive Japanese CRC6 Enable (RJC).
Bit 2/Receive Side ZBTSI Support Enable (RZBTSI). Allows ZBTSI information to be output on RLINK pin.
Bit 3/Receive FDL Zero Destuffer Enable (RZSE). Set this bit to zero if using the internal HDLC/BOC controller instead of
the legacy support for the FDL. See Legacy FDL Support (T1 Mode) for details.
Bit 4/Receive SLC–96 Enable (RSLC96). Only set this bit to a one in SLC-96 framing applications. See D4/SLC–96
Operation for details.
Bit 5/Receive B8ZS Enable (RB8ZS).
Bit 6/Receive Frame Mode Select (RFM).
Bit 7/Unused, must be set to zero for proper operation.
0 = zeros in bit 2 of all channels
1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
0 = ZBTSI disabled
1 = ZBTSI enabled
0 = zero destuffer disabled
1 = zero destuffer enabled
0 = SLC–96 disabled
1 = SLC–96 enabled
0 = B8ZS disabled
1 = B8ZS enabled
0 = D4 framing mode
1 = ESF framing mode
7
—
0
RFM
T1RCR2
T1 Receive Control Register 2
04h
6
0
RB8ZS
5
0
RSLC96
4
0
54 of 269
RZSE
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
RZBTSI
2
0
RJC
1
0
RD4YM
0
0