DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 239

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled)
NOTES:
1) RCHBLK is programmed to block channel 1.
2) RLCLK is programmed to mark the Sa4 bit in RLINK.
3) Shown is a RNAF frame boundary.
4) RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1.
RCHBLK
RFSYNC
RCHCLK
RSYNC
RLINK
RLCLK
RSER
RCLK
RSIG
1
2
CHANNEL 32
CHANNEL 32
A
B
C
LSB
D
Si
1
239 of 269
A Sa4 Sa5 Sa6 Sa7 Sa8
Sa4 Sa5 Sa6 Sa7 Sa8
CHANNEL 1
CHANNEL 1
Note 4
DS21455/DS21458 Quad T1/E1/J1 Transceivers
MSB
CHANNEL 2
CHANNEL 2
A
B

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