DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 266

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DS21458LDK

Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
6) No relationship between TCHCLK and TCHBLK and the other signals is implied.
NOTES:
1) TSYNC is in the output mode (TCR2.2 = 1).
2) TSYNC is in the input mode (TCR2.2 = 0).
3) TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
4) TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.
5) TLINK is only sampled during F-bit locations.
Figure 38-13. Transmit Side Timing
TSER / TSIG /
TDATA
TCHCLK
TCHBLK
TSYNC
TSYNC
TCLK
TESO
TLCLK
TLINK
1
2
5
t R
t D2
t
D1
t D2
t D2
F t
t SU
t
SU
t D2
266 of 269
t SU
t
HD
t
HD
t HD
DS21455/DS21458 Quad T1/E1/J1 Transceivers
t
CL
t
CP
t
CH

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