DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 196

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3/Error Insertion Rate Select Bits (ER0 to ER3).
Bit 4/Constant Errors (CE). When this bit is set high (and the ER0 to ER3 bits are not set to 0000), the error insertion logic
will ignore the number of error registers (NOE1, NOE2) and generate errors constantly at the selected insertion rate. When CE
is set to zero, the NOEx registers determine how many errors are to be inserted.
Bit 5/Unused, must be set to zero for proper operation.
Bit 6/Unused, must be set to zero for proper operation.
Bit 7/Write NOE Registers (WNOE). If the host wishes to update to the NOEx registers, this bit must be toggled from a zero
to a one after the host has already loaded the prescribed error count into the NOEx registers. The toggling of this bit causes the
error count loaded into the NOEx registers to be loaded into the error insertion circuitry on the next clock cycle. Subsequent
updates require that the WNOE bit be set to zero and then one once again.
ER3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ER2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WNOE
7
0
ER1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ER0
—
ERC
Error Rate Control Register
EBh
6
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No errors inserted
1 in 16
1 in 32
1 in 64
1 in 128
1 in 256
1 in 512
1 in 1024
1 in 2048
1 in 4096
1 in 8192
1 in 16,384
1 in 32,768
1 in 65,536
1 in 131,072
1 in 262,144
ERROR RATE
—
5
0
CE
4
0
196 of 269
ER3
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
ER2
2
0
ER1
1
0
ER0
0
0