DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 71

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

12. COMMON CONTROL AND STATUS REGISTERS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Function of the RLOS/LOTC Output (RLOSF).
Bit 1/Transmit Clock Source Select Bit 0 (TCSS0).
Bit 2/Transmit Clock Source Select Bit 1 (TCSS1).
Bit 3/Unused, must be set to zero for proper operation.
Bit 4/Output Data Mode (ODM).
Bit 5/Signaling Integration Enable (SIE).
Bit 6/CRC-4 Recalculate (CRC4R) (E1 Only).
Bit 7/MCLK Source (MCLKS). Selects the source of MCLK.
TCSS1
0
0
1
1
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
0 = pulses at TPOSO and TNEGO are one full TCLKO period wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
0 = signaling changes of state reported on any change in selected channels
1 = signaling must be stable for three multiframes for a change of state to be reported
0 = transmit CRC-4 generation and insertion operates in normal mode
1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method
0 = MCLK is sourced from the MCLK pin
1 = MCLK is sourced from the TSYSCLK pin
TCSS0
MCLKS
0
1
0
1
7
0
The TCLK pin is always the source of transmit clock.
Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition
after one channel time.
Use the scaled signal present at MCLK as the transmit clock. The TCLK pin is ignored.
Use the signal present at RCLK as the transmit clock. The TCLK pin is ignored.
CRC4R
CCR1
Common Control Register 1
70h
6
0
SIE
5
0
TRANSMIT CLOCK SOURCE
ODM
4
0
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3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TCSS1
2
0
TCSS0
1
0
RLOSF
0
0