DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 241
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz
(With Elastic Store Enabled)
NOTES:
1) RSYNC is in the output mode (IOCR1.4 = 0).
2) RSYNC is in the input mode (IOCR1.4 = 1).
3) RCHBLK is programmed to block channel 1.
4) RSIG normally contains the CAS multiframe-alignment nibble (0000) in channel 1.
RSYSCLK
RCHBLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RSER
RSIG
2
1
3
CHANNEL 31
A
CHANNEL 31
B
C
LSB MSB
D
241 of 269
CHANNEL 32
A
DS21455/DS21458 Quad T1/E1/J1 Transceivers
CHANNEL 32
B
C
LSB MSB
D
CHANNEL 1
CHANNEL 1
Note 4
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