DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 76

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250s at the beginning of align frames. Used to alert the host
that Si and Sa bits are available in the RAF and RNAF registers.
Bit 1/Receive CRC-4 Multiframe Event (RCMF) (E1 Only). Set on CRC-4 multiframe boundaries; will continue to be set
every 2ms on an arbitrary boundary if CRC-4 is disabled.
Bit 2/Receive Multiframe Event (RMF).
E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the
host that signaling data is available.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
Bit 3/Transmit Align Frame Event (TAF) (E1 Only). Set every 250s at the beginning of align frames. Used to alert the
host that the TAF and TNAF registers need to be updated.
Bit 4/Transmit Multiframe Event (TMF).
E1 Mode: Set every 2ms (regardless if CRC-4 is enabled) on transmit multiframe boundaries. Used to alert the host that
signaling data needs to be updated.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
Bit 5/Receive Signaling All Zeros Event (RSA0) (E1 Only). Set when over a full MF time slot 16 contains all zeros.
Bit 6/Receive Signaling All Ones Event (RSA1) (E1 Only). Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 7/Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI
T1.403.
RAIS-CI
7
0
RSA1
SR4
Status Register 4
1Ch
6
0
RSA0
5
0
TMF
4
0
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TAF
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
RMF
2
0
RCMF
1
0
RAF
0
0