DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 229
DS21458LDK
Manufacturer Part Number
DS21458LDK
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS21458LDK.pdf
(269 pages)
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Figure 36-2. Receive Side ESF Timing
NOTES:
1) RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0).
2) RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1).
3) RSYNC in multiframe mode (IOCR1.4 = 1).
4) ZBTSI mode disabled (T1RCR2.2 = 0).
5) RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames.
6) ZBTSI mode is enabled (T1RCR2.2 = 1).
7) RLINK data (Z bits) is updated one bit time before odd frames and held for four frames.
FRAME#
RFSYNC
RSYNC
RLCLK
RSYNC
TLCLK
RSYNC
RLINK
TLINK
4
5
6
1
2
3
7
1
2
3
4
5
6
7
8
9 10 11 12
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
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