DS21458LDK Maxim Integrated, DS21458LDK Datasheet - Page 74

• Manufacturer Part Number: DS21458LDK
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI
Bit 1/Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has been set for
two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
Bit 2/V5.2 Link Detected Condition (V52LNK) (E1 Only). Set on detection of a V5.2 link identification signal. (G.965).
Bit 3/Loss of Receive Clock Condition (LORC). Set when the RCLKI pin has not transitioned for one channel time.
Bit 4/Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for one channel time. Will
force the LOTC pin high if enabled via CCR1.0.
Bit 5/Loop-Up Code Detected Condition (LUP) (T1 Only). Set when the loop up code as defined in the RUPCD1/2 register
is being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
Bit 6/Loop-Down Code Detected Condition (LDN). (T1 only) Set when the loop down code as defined in the RDNCD1/2
register is being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
Bit 7/Spare Code Detected Condition (LSPARE). (T1 only) Set when the spare code as defined in the RSCD1/2 registers is
being received. See the Programmable In-Band Loop Code Generation and Detection section for details.
LSPARE
7
0
LDN
SR3
Status Register 3
1Ah
6
0
LUP
5
0
LOTC
4
0
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LORC
3
0
DS21455/DS21458 Quad T1/E1/J1 Transceivers
V52LNK
2
0
RDMA
1
0
RRA
0
0