ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 119

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ATAVRSB202

Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Datasheets

Specifications of ATAVRSB202

Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20.3.2
8042B–AVR–06/10
Cell inputs
The V-ADC features one input channel for each battery cell to be able to measure each cell indi-
vidually and to measure the total battery voltage through the input pins NV, PV1, PV2, PV3 and
PV4. Note that the internal Cell Balancing uses the same pins to bypass balancing current
”Cell Balancing” on page
the V-ADC should not do conversion on the selected channel, as the internal Cell balancing will
affect the conversion result.
The V-ADC is designed to operate on PV1 pin voltages above 2V. If the battery cell voltage on
PV1 input falls below 2V the upper cell voltage appears to be lower than the its actual value. To
avoid that cells get potentially overcharged software should keep the cells in balance using the
internal Cell Balancing.
When not using all the cell inputs, the unused cells should be connected to the cell below. An
example external coupling in 3-cell mode is shown in
the input is not used, it is recommended to connect the input through an external resistance to
limit inverse coupling current. This is to be able to protect the battery if cells are reversed cou-
pled during production.
Figure 20-3. 1 3-cell mode connection
R
R
R
R
R
See ”Cell Balancing” on page 154.
154.) for details for balancing the battery cells. When balancing a cell
C
C
C
PV4
PV3
PV2
PV1
NV
ATmega16HVB/32HVB
ATmega16HVB/32HVB
Figure 20-3 on page
for details.
119. Note that even if
(See
119

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