ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 162
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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27.5
27.5.1
8042B–AVR–06/10
Overview of the TWI Module
SCL and SDA Pins
The TWI module is comprised of several submodules, as shown in
isters are accessible through the AVR data bus.
Figure 27-9. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns.
Address Match Unit
Slew-rate
Arbitration Detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
ATmega16HVB/32HVB
State Machine and
Control Unit
Status Control
Control Register
Figure
Bit Rate Generator
(TWCR)
Bit Rate Register
Prescaler
(TWBR)
27-9. The shaded reg-
162
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