ATAVRSB202 Atmel, ATAVRSB202 Datasheet - Page 140
ATAVRSB202
Manufacturer Part Number
ATAVRSB202
Description
KIT BATT MGMT FOR ATMEGA32HVB
Manufacturer
Atmel
Specifications of ATAVRSB202
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.6
24.7
24.7.1
8042B–AVR–06/10
Battery Protection CPU Interface
Register Description
BPPLR – Battery Protection Parameter Lock Register
The Battery Protection CPU Interface is illustrated in
Figure 24-2. Battery Protection CPU Interface
Each protection originating from the Current Battery Protection module has an Interrupt Flag.
Each Flag can be read and cleared by the CPU, and each flag has an individual interrupt enable.
All enabled flags are combined into a single battery protection interrupt request to the CPU. This
interrupt can wake up the CPU from any operation mode, except Power-off. The interrupt flags
are cleared by writing a logic ‘1’ to their bit locations from the CPU. An interrupt event for the
External Protection Input can be generated by enabling the external interrupt for the input port.
• Bit 7:2 – Reserved
These bits are reserved and will always read as zero.
• Bit 1 – BPPLE: Battery Protection Parameter Lock Enable
• Bit 0 – BPPL: Battery Protection Parameter Lock
The BPCR, BPHCTR, BPOCTR, BPSCTR, BPDHCD, BPCHCD, BPDOCD, BPCOCD and
BPSCD Battery Protection registers can be locked from any further software updates. Once
Bit
(0xFE)
Read/Write
Initial Value
Battery Protection
Parameter Lock
Register
EXTPROT
PPI
NNI
R
7
–
0
Battery Protection
Level Register
LOCK?
R
6
–
0
Battery Protection
R
Timing Register
5
–
0
Protection
Current
Battery
LOCK?
R
4
–
0
Battery Protection
Control Register
LOCK?
ATmega16HVB/32HVB
Figure 24-2 on page
R
3
–
0
Power-off
R
2
–
0
Interrupt
Request
BPPLE
Protection
R/W
Current
1
0
140.
8-BIT DATA BUS
Acknowledge
Protection
Interrupt
Interrupt
Register
10
Battery
Control
/
FET
BPPL
R/W
0
0
5
5
/
/
BPPLR
140
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